I hope you've got some time left as we still have to check out the internals of the Wii U, starting with the central chip.
Origins and hypotheses
Since the Wii U was announced (then known as Project Cafe), there's been significant speculation about what would the new CPU be made of. At some point, journalists speculated that Nintendo would embrace a modern version of IBM's POWER line . I guess audiences were expecting a ground-breaking CPU as Cell and Xenon proved six years before. Moreover, with the decline of PowerPC (most apparently with Apple switching to Intel Core in 2006), the idea that any new CPU from IBM would come as a derivative of POWER wasn't too far-fetched.
Well, there is one fault with the previous logic, which is that Nintendo doesn't favour emerging technology. Their formula focuses instead on grabbing existing technology and finding innovative and clever uses. This is not necessarily a bad characteristic, as Nintendo engineers have been very clever in showing state-of-the-art applications with technology deemed 'outdated'. Take a look at the Z80-hybrid of a Game Boy, or the under-clocked ARM9 on the Nintendo DS, or even the partially-updated GameCube called 'Wii'. If there's something common among all of these, is that all have broken sales records. Now, will the Wii U be part of that club? You'll be the judge of that.
The 8th-generation architecture
In the past generation, Sony and Microsoft made strong bets (some riskier than others) on contemporary technologies at a reduced cost. With the Wii U, Nintendo looked at a slightly different direction, focusing on low-cost, low-power consumption and backwards compatibility . The latter will have a strong impact on the final design of this console. Consequently, the new CPU doesn't deliver any radical component and instead tries to catch up with the latest advancements in the industry (multi-core processing, GHz speeds, etc).
That being said, Nintendo partnered with IBM to deliver their new CPU. The result was Espresso and runs at 1.24 GHz .
Now, let's bring Espresso forward:
Overview of Espresso.
... and as with any other article in this series, I'll explain how it works.
Familiar faces
Before we start the real analysis, let me go back to the previous diagram. As you've seen there, Espresso is a symmetric multi-core system, just like Xenon. But that's not all, as each of Espresso's cores appears to be a replica of IBM's Broadway, the exact same core used with the Wii (which in turn, is a tweaked version of Gekko, found in the GameCube).
Study of Espresso
We'll now take a look at how Espresso is constructed. As I've already explained how Broadway and Gekko work, I'll focus on the novelties of Espresso, namely its multi-core layout, cache system and memory.
At this point, it's fair to say that neither Nintendo nor IBM have publicly documented the inner workings of Espresso (unlike Xenon and Cell from which many IBM engineers published papers on IBM's now-defunct developerWorks portal). I guess that neither planned to commercialise Espresso outside the Wii U. As a consequence, this section has been possible due to the countless hours spent by hacking groups like fail0verflow (a.k.a Team Twiizers) which not only managed to reverse-engineer this system, but also take the time to publish documentation about it (don't forget to look at the cited documents if you enjoy the topic). For this study, I've combined third-party research with public information from IBM (related to Broadway) and Freescale, and the result is what you see below.
'Multi-coring' Broadway
The big SoC (housing Espresso, among others) next to four 512 MB DDR3 chips
Espresso bundles three CPU cores based on the PowerPC 750CXe architecture. The design of these dates all the way back to 2001, meaning that the datapath and instruction set are roughly in the same state as they were 10 years before. For comparison, the PowerPC Processing Element (the main core of Xenon and Cell) grabbed the design of the POWER4 and re-engineered it for the requirements of the respective console.
Moving on, Espresso implements a symmetric multi-core layout... but how is this possible with those old cores? Well, in a (now defunct) FAQ portal, IBM has explained that the 750 already supports a multi-processing environment , it just needs extra work for maintaining cache integrity (between the different L1, L2 and the TLB). However, doing this through software cancels out the advantages of having a multi-processor design, so the idea was never taken forward... That is, until Nintendo reached IBM again.
In the end, IBM grabbed three Broadway CPUs, stepped up the clock to 1.24 GHz and wrapped them with extra L2 cache and the necessary circuitry to arbitrate bus contention and cache coherency (so it doesn't have to be done with software). That's Espresso.
A recallable bus
Layout of the internal cores of Espresso
The external bus that connects the CPU cores with external components has an interesting history, dating back to 1993, with the launch of the Motorola 88110. After the formation of the AIM alliance, IBM and Motorola created a joint CPU based on their best inventions. IBM contributed with their POWER architecture and Motorola chipped in with the bus design of their 88110 CPU. In 1993, the PowerPC 601 was unveiled.
The PowerPC 601 featured a bus protocol called 60x bus. This was quite advanced and flexible for the time, already supporting 64-bit operations, fast clock speeds, cache coherency and multiprocessor configurations (hence the fact IBM stated the 750 could work with multi-CPUs right away) . All of this reminds me of the anticipation of the Hitachi SH-2.
Back to the Wii U, IBM grabbed the 60x bus again to interconnect the three cores in Espresso. Additionally, they implemented a variant of the bus to connect Espresso (as a chip) with the rest of the motherboard.
If you wonder about the current adoption of the 60x bus, I'm afraid it's been long superseded by an improved protocol called 'MPX' which Motorola implemented for their PowerPC 74xx line (also known as 'G4'). The MPX bus solves deficiencies of the 60x like slow data throughputs with the use of 'data streams' to reduce wait states . IBM, on the other side, presented their 'Elastic Interface' bus with their PowerPC 970 line (G5) and POWER4 .
More cache
With the Wii (and GameCube), Broadway/Gekko only disposed of 256 KB of L2 cache and 64 KB of L1 cache. With the Wii U, L1 cache stays the same with each core of Espresso, but two of them are now provided with 512 KB of L2 cache and the third's got a whopping 2 MB of L2. In reality, this doesn't mean there's 2.5 MB of 'practical' cache, as different cores may need to cache the same portion from RAM, something that wouldn't happen if cache were shared (but then, other problems would arise!).
All L2 caches found in Espresso are 4-way associative. Compare this to the 8-way associations in Xenon and Cell, which in the case of Xenon, was meant to alleviate the 3 cores competing for 1 MB of shared L2. With Espresso, iterating through cache associations will take less time, but there will be more frequent cache misses.
To handle cache coherency between the three independent L2 cache blocks, Espresso's internal Bus Interface abides by the MERSI protocol (same as Cell/Xenon). For reference, Broadway (a single-core system) used the MEI protocol.
As a side note, L2 memory in Espresso is of type eDRAM, as opposed to SRAM. Furthermore, the L1 block still offers locked and RAM-to-L1 DMA instructions (as the GameCube's CPU did).
Room for improvement
As emphasised by fail0verflow, the Wii U, as a system, is in fact not cache coherent. External I/O can alter memory without the awareness of Espresso, therefore cache is not automatically refreshed in those situations. By contrast, the Xbox 360's Southbridge notifies the caches after peripherals DMA to main RAM.
Moreover, two existing PowerPC instructions made for multi-processing environments, lwarx (Load Word and Reserve Indexed) and stwcx (Store Word Conditional Indexed), no longer function as intended. As fail0verflow also noted , these now need a manual cache flush to work as intended. At least it's not the first PowerPC variant to ship with broken instructions (see Xbox 360's xdcbt).
It's not all bad news, luckily. At least Espresso inherits Gekko's ability for out-of-order instruction execution, something that had to be cut from Xenon and Cell.
Memory Available
This section is simple and complicated at the same time. In summary, there are three places to store volatile data:
- A hefty chunk of 2 GB of DDR3 SDRAM called MEM2.
- A smaller block of 32 MB of EDRAM named MEM1.
- An even smaller piece of 3 MB of 1T-SRAM called MEM0.
The reason for such disparity is that you may remember MEM1 and MEM0 from the times of the Wii and GameCube. They've been carried forward with the Wii U, albeit with a slight increase of MEM1.
Memory layout of general-purpose memory (in 'Wii U' mode).
In any case, from the developer's point of view, only MEM2 and MEM1 (the two bigger blocks) are accessible. The 2 GB of DDR3 may hold any kind of data (supplying both CPU and GPU), while the other two have more limited functions. MEM1 is used for graphics data (more details in the 'Graphics' section) and MEM0 is used by the operating system (more details in the 'Operating System' section).
In some ways, this system follows the Unified Memory architecture (UMA). Though, with MEM1 and MEM2 in the middle, I wouldn't say this system is fully compliant with the UMA model (unlike some of its competitors).
GDDR3 or DDR3?
The old Wii employed GDDR3 memory, which is particularly fast for graphics operations. The Wii U's choice is not only larger but also features a new type called DDR3 (without the 'G' at the start). Does this mean the Wii U has been downgraded? Confusingly enough, no.
GDDR3 memory is an improved version of DDR2 for graphics-related functions. Years later saw the arrival of DDR3, which succeeds both DDR2 and GDDR3. Have I lost you already? Well, to make matters more baffling, the follow-up GDDR4 and GDDR5 are enhancements over DDR3 and no other.
The nomenclature is unnecessarily deceptive. But let's not lose our focus, the Wii U employs DDR3 and that means higher bandwidth compared to the Wii's GDDR3.
Becoming a Wii
I'm eager to say that, while the new hardware may look underwhelming in some areas, the logic behind Wii backwards compatibility reaches the same level of dedication as the Nintendo DS or Game Boy Advance.
The methodology applied shares the same principles of those two consoles as well. Instead of resorting to software emulation or provisional hardware, the Wii U has been built as a superset of the Wii. Thus, it can easily replicate the hardware of the Wii by just hiding its modern features.
Having said that, whenever the Wii U decides to 'become a Wii', Espresso deactivates two of its cores (leaving a single Broadway core) and MEM2 hides 1984 MB of RAM (leaving the previous amount of 64 MB). Once in 'Virtual Wii' (vWii) mode, the old Wii game can safely assume it's running on top of a real Wii.
There are more nooks and crannies behind this compatibility mode involving obscure I/O (explained in due time), so keep on reading if you are curious about this process!
The last venture of PowerPC
As we reach the end of the CPU section, it looks like this will be my last analysis of a PowerPC-based system (at least chronologically, I haven't talked about the Apple Pippin yet).
The PowerPC has been an interesting development, with its ups and downs. And while it didn't manage to dethrone x86, it did conquer three generations of consoles.
In any case, our beloved Espresso is, at its essence, a modern improvement to a fundamentally outdated platform. Both IBM and Motorola already dismissed the 750CL line in favour of the 7400 and the 970 lines, respectively. Yet, it's curious to see how IBM had to dig up their old designs to produce a console that could compete in the 2010s. I guess the lack of a consumer version of Espresso is proof that IBM wasn't interested in pushing Espresso any further.
But hey, just like with Xenon or Cell, it's all part of an evolutionary line. I don't believe these kinds of technologies are forgotten or abandoned, but their designs and expertise eventually merge into other projects.