To be blunt, the main program is written in plain 65816 assembly and the music driver is written in SPC700 assembly. Needless to say, you won't find any of the comforts available on 21st-century equipment.
There were, however, some tools distributed by Nintendo, Intelligent Systems and Ricoh to make life easier for programmers, these included :
- Different types of development units, capable of being controlled by a debugger from a host machine (typically running MS-DOS).
- Flashable cartridges (a.k.a. Flashcarts) - not for piracy, but to enable developers test their code on retail units.
- 65816 and SPC700 assemblers.
- Development Manuals explaining from a low-level perspective how this console works. These often included guidelines and norms that developers had to follow to get their game approved by Nintendo (necessary for distribution).
Curiously enough, several game studios - including Argonaut Software, Accolade, and SN Systems - developed custom in-house equipment, often providing more capabilities than the official offerings (e.g. memory editors, floppy disk readers, ISA-based devkits, etc.) .
Cartridge configuration
When it comes to accessing the cartridge, things get a lot more confusing compared to the relatively simpler mapping model of the NES. I find it interesting nonetheless, especially for understanding how it could be expanded.
The 65C816 features a 24-bit address bus, enabling to access up to 16 MB worth of data. However, due to the console's architecture, a portion of the address space is reserved for memory-mapped components. Moreover, the 65C816 only comes with 16 address lines, which are then combined with internal registers to construct a 24-bit address. This is analogous to housing an internal mapper and requiring bank switching to access extra data beyond the boundaries of the address bus. If you explore other systems of the same generation, you'll find this methodology somewhat familiar.
Example cartridge boards designed with different configurations .
From top to bottom: LoROM (dual ROM with battery-backed SRAM), LoROM (single ROM with battery-backed SRAM) and LoROM (single ROM)
That being said, when it comes to designing a cartridge, there are many ways to electrically connect the address pins between the ROM and CPU, each utilising bank switching in a different way.
There are two fundamental models that enable accessing up to 4 MB of ROM and 64 KB of SRAM , and they work as follows:
- With the LoROM Model, ROM Data is arranged in 32 KB chunks with 128 banks available to choose from . SRAM, though fitting within two banks, is accessible across 15 banks, where ROM data is also present.
- This setup requires frequent bank switching during execution. On the other hand, half of the banks are also mapped to WRAM, meaning ROM, SRAM, and WRAM can be accessed without switching banks.
- With the HiROM Model, ROM space is structured into full banks, meaning data is stored in 64 KB chunks across 64 banks. This configuration reduces the need for bank switching, but at the cost of not being able to read ROM, WRAM and SRAM within the same bank.
In both cases, a significant portion of ROM space is mirrored across the leftover area of the CPU's address space. However, here's the interesting part: one half of the space operates at ~2.68 MHz while the other can reach 3.58 MHz - but only if the ROM chip supports the higher speed and the CPU's FastROM flag is enabled .
Additionally, cartridges that bundle SRAM must house a MAD-1 (or similar) chip, which performs address decoding. This component is particularly crucial for correctly latching the pins that select between ROM and SRAM chips .
Beyond convention
Now, when programmers require more space, derivative models of LoROM and HiROM come into place. Two common variations, known as ExHiROM and ExLoROM, extend the ROM's addressing space by reducing the mirrored area. Both can access ~7.9 MB of ROM.
Star Fox (1993) uses the Super FX GSU chip to render 3D surfaces. Behind the scenes, the S-PPU only sees a background layer made of erratic tiles.
Alternatively, and most importantly, LoRom and HiROM can also be adapted to accommodate enhancement chips within the cartridge. These are additional processors that expand the capabilities of the console. To name a few examples of new configurations:
- The MMC model enables bank switching via the local enhancement chip. This was used by components like the S-DD1 or the SPC7110, both function as hardware tile decompressors.
- The Super Accelerator System model was designed for the highly regarded SA-1, a secondary 65C816-based CPU operating at 10.74 MHz with extra functionality. It builds upon the MMC model, incorporating new circuitry for the additional memory-mapped components.
- Two extra configurations - one based on LoROM and the other on HiROM - make way for the DSP series. These chips are derivatives of the NEC µPD77C25 CPU, but running a different program. They provide vector and matrix computations . Various games have used them for affine transformations, graphics decompressing and shortest path calculations.
- The SFX model targets the popular Super FX GSU chip. This configuration maps up to 8 MB of ROM, with 2 MB shared between the main CPU and the Super FX. The rest of the address space includes additional backup RAM and SRAM. Developed by Argonaut, the Super FX is a proprietary processor specialising in 3D surface rendering and 2D affine transformations. The processed graphics are then streamed as tiles for the S-PPU to display. Several notable games leveraged this technology to render 3D models and extend Mode 7 for sprites (as Mode 7 can only transform backgrounds).
It's difficult to overlook the impact this engineering had on 90s gaming, with many titles surpassing the console's expectations - and without requiring expansion modules and whatnot. You could say this complicated Nintendo's plans for a successor console, which may explain the cancellation of advanced games like Star Fox 2.