The Super Nintendo's choice of processor is a peculiar one. Unlike its competition bundling a fully-fledged 68000, the SNES' chip is not a radical departure from its predecessor. To recap, the NES employed a modified 6502 CPU, an admired ingredient of late-70s and early-80s computers. Now, to pave the way for the new decade (the 90s), Nintendo opted for a more conservative (and cheaper) solution: the WDC 65C816, a 16-bit extension of the 6502.
Modernising the 6502
The 65C816 CPU originates from Western Design Center (WDC), particularly from Bill Mensch, a former member of the 6502 team (at MOS) and the 6800 team (at Motorola). In 1978, one year after leaving MOS, Mensch founded Western Design Center, a semiconductor company that produces clones of the MOS 6502 with attractive enhancements (e.g., CMOS design, extra opcodes, circuitry fixes, new addressing modes, etc.).
The WDC 65C816 chip found on the Apple IIGS.
One day, Apple approached WDC to design a backwards-compatible variant of the 6502 that could process larger amounts of data. This resulted in the WDC 65C816 CPU, released in 1983. Curiously enough, Apple encountered many setbacks during the development of a computer that would use the new CPU, until three years later, with the release of the Apple IIGS.
In the end, the Apple IIGS and the Super Nintendo became the only major adopters of the 65C816 CPU.
Meanwhile, Nintendo was enjoying a good relationship with Ricoh and their set of bespoke chips for the NES. I haven't found the exact document outlining what connected Ricoh to WDC, but what I can confirm is that at some point in time, WDC agreed to license their 65C816 designs to Ricoh . Consequently, the latter tailored it to meet the new requirements of the Super Nintendo, it became the Ricoh 5A22 and was exclusively supplied to Nintendo.
The new CPU
As you've seen before, the main processor of this console is the Ricoh 5A22, a superset of the 65C816.
The Ricoh 5A22 chip, labelled 'S-CPU' by Nintendo.
Unlike the Apple IIGS, which enjoyed backward compatibility with Apple II software, the Super Nintendo is not compatible with NES games. To be fair, based on the choice of processor, there's a slight possibility that the SNES was originally planned to be compatible with NES games, who knows.
Moving on, the CPU employs a variable clock speed, reaching up to 3.58 MHz for register operations and dropping to 1.79 MHz when accessing the slowest buses (i.e. the serial/controller port).
Now, to properly understand the functionality of the 5A22, we must first look at what the 65C816 provides:
- The 65816 Instruction Set Architecture (ISA): The debut 16-bit instruction set of the 65C816. It is based on the 6502 ISA but does not implement undocumented instructions that some NES games resorted to .
- The size of instructions can vary between 1 byte (8 bits) and 4 bytes (32 bits), depending on how memory addresses are referenced (a.k.a. the 'addressing mode' used) .
- The broken Binary-Coded Decimal (BCD) mode is functional again (I'm guessing as a consequence of appropriate licensing).
- 10 different modes of operation: Due to a combination of backwards compatibility with the 6502, the return of the BCD mode (missing on the NES), and the ability to switch between groups of 16-bit and 8-bit registers , developers can utilise this CPU using different combinations of these.
- Unlike later MIPS CPUs, there isn't a mixed instruction set with dedicated opcodes for 8-bit and 16-bit words. Instead, the same instruction set is interpreted differently depending on the mode activated.
- For compatibility reasons, the CPU always starts in 'emulation' mode (pure 6502), and it is up to the program to switch to a particular 'native' mode to enable 16-bit functionality. On a side note, it is amusing how Intel's x86 still follows the same modus operandi in their modern CPUs.
- Three 16-bit general-purpose registers. This set matches the 6502's (
X,YandA). However, due to the different modes of operation, these registers can now switch between 16-bit and 8-bit.- Compare this number to the sixteen 32-bit registers the competition offered - quite a contrast!
- 16-bit internal data bus and an 8-bit external data bus: This results in performance penalties when moving values larger than 8 bits across memory (as the CPU requires additional cycles), a common occurrence considering most instructions are 16-bit long. However, the overall impact is alleviated thanks to Ricoh's DMA units (explained later on) and the variable clock speed.
- 24-bit address space: Allows the CPU to access up to 16 MB worth of memory. This is similar to the Motorola 68000, except the 65C816 obtains its 24-bit addresses by combining extra 8-bit registers (
DBRandPBR) with the original 16-bit addressing lines of the 6502 . Overall, this methodology is similar to housing an internal mapper.
Looking at this, I have to confess that the 65C816 feels excessively cumbersome for little gain. Compared to other offerings such as the Motorola 68000, it is not difficult to conclude why the Apple IIGS remained the only personal computer to adopt the 65C816. Nonetheless, throughout this article, you will see how Nintendo and Ricoh managed to turn the limitations of this CPU into opportunities to revamp its game library.
Ricoh's additions
In 1983, the 65C816 CPU was conceived as a general-purpose successor of its 1975 ancestor, with all the associated requirements and constraints. Yet, Nintendo planned its console to last throughout the 90s, meaning Ricoh had to step up its game (if you'll pardon the pun).
First on the list was tackling its arithmetic limitations - the 65C816 lacks dedicated instructions for multiplication or division. As a result, Ricoh incorporated multiplication and division units, enabling the CPU to perform these types of operations via hardware (rather than software). Instead of conventional instructions, they are operated through registers.
The multiplier receives 8-bit numbers and outputs 16-bit ones . Conversely, the divider takes a 16-bit dividend and an 8-bit divisor; and returns a 16-bit quotient along with a 16-bit remainder . Both units only support positive numbers (called 'unsigned').
Now, you may be wondering 'why is this relevant?'. The significance of these additions will become clear when we explore the novelties of the Super Nintendo's graphics chips (in the 'Graphics' section).
Speedy memory access
The second challenge was to increase its data bandwidth. Hence, two exclusive DMAs (Direct Memory Access) were added to move data around without the intervention of the CPU, resulting in faster speeds. For this design to work, regions of memory are referenced using two distinct address buses :
- A 24-bit 'A Bus' controlled by the CPU: Connects the cartridge, CPU, and WRAM.
- An 8-bit 'B Bus' controlled by the S-PPU: Connects the cartridge, CPU, WRAM, S-PPU, and the Audio CPU.
When setting up a DMA transfer, the origin bus must differ from the destination bus.
Furthermore, the two DMAs are not identical and serve very distinct functions :
- The General-Purpose DMA performs transfers at any time, temporarily halting the CPU until the transfer is finished.
- The Horizontal DMA (HDMA) performs a small transfer after each horizontal scan (while the CRT beam is preparing to draw the next row). This prevents prolonged CPU interruption, but transfers are limited to 4 bytes per scanline.
Finally, the system provides eight channels for DMA transfers, enabling to dispatch up to eight independent transfers at once.
The 16-bit Segmentation Fault
The primitive Open Bus behaviour is also present in this console. Furthermore, there has been speculation about the existence of an internal register called Memory Data Register (MDR), which is believed to store such values .
For comparison, the 68000 employs a vector table to handle exceptions, ensuring execution is redirected whenever a fault is detected.
(Lots of) more memory
It's fascinating to realise how much content the NES managed to display with only 2 KB of RAM. Well, the Super Nintendo now features 128 KB of RAM (still referred to as 'Work RAM' or WRAM) - a staggering 6400% increase in general-purpose memory compared to its predecessor.
Be that as it may, while the NES enjoyed the fast Static RAM (SRAM) type, Nintendo opted to use Dynamic RAM (DRAM) for the Super Nintendo's WRAM. Dynamic, in this case, means memory needs to be refreshed periodically. The 5A22 performs this automatically, but during each refresh operation, the CPU is paused. This causes an overall CPU slowdown of roughly 3% .
That said, what can developers do with this memory? Anything they desire, really. WRAM is used to store variable data for the game. The more space available, the greater the amount of information that can be stored and processed (thus, reducing reliance on cartridge hardware).
However, as the following sections will demonstrate, the Super Nintendo is a fairly complex machine (albeit with its 'simplistic' CPU). I tend to call this console a 'collection of mini-computers/subsystems'. Each subsystem may need data from the CPU, meaning programmers may reserve portions of WRAM to process that information - thus justifying the need for 128 KB of memory.