Just like its close competitors drowned in options during the RISC fever, Sega had to go through all the conundrums of choosing a new vendor that could deliver the next generation of games (including those with '3D' capabilities). In the end, the company chose a fresh CPU whose creator was desperately seeking an adopter: the Hitachi SuperH, or 'SH'.
While initially focused on embedded applications, Hitachi's new creation debuted modern arts such as :
- A load-store architecture, meaning instructions don't mix memory and register operations, resulting in a cleaner and scalable CPU design. This is one of the pillars of RISC CPUs.
- A 32-bit data bus and Arithmetic Logic Unit (ALU), enabling the flow and operation of larger amounts of data (32-bit values) without consuming extra cycles.
- 16 general-purpose 32-bit registers, this time more flexible than those found in previous CPUs, such as the Motorola 68000. This is another design decision derived from the RISC guidelines .
- 32-bit address bus, allowing up to 4 GB of memory to be addressed (farewell mappers).
- A pipelined data path with five stages: The execution of instructions is now divided into five steps, or stages. The CPU can queue up to five instructions simultaneously, with each one assigned to a different stage. This allows taking advantage of all the CPU's resources without idling, while also increasing the number of instructions processed per unit of time.
- A 16-bit multiplication unit: Performs multiplications with 16-bit integers.
Furthermore, the SuperH features a new instruction set called SuperH ISA which, apart from adopting a RISC design, all of its instructions are 16 bits wide. This comes as a surprise since this CPU operates 32-bit words, so you would expect instructions to have the same length. Yet, Hitachi managed to fit its ISA using half the size. Not only does this format reduce the size of programs, but since the CPU fetches instructions in 32-bit batches, two instructions can be retrieved in one cycle. Overall, this technique of compressing the instruction set helped tackle a common concern of RISC-based architectures called 'code density', where the latter required more instructions (therefore, more memory) to perform the same tasks as non-RISC systems.
The ramifications
Conversely, other drawbacks of RISC designs are still present in the SuperH, such as control hazards. Consequently, programs are required to include branch delay slots to avoid calculation errors. To remedy things, the SuperH features delayed branch instructions which are branch instructions pre-fitted with a delay slot .
Data hazards are also present but not tackled by the programmer or compiler; the CPU will automatically stall the pipeline whenever necessary.
Sega is not satisfied
Nevertheless, all of that didn't stop Sega from expressing dissatisfaction with the end product. This was mainly due to the small 16-bit multiplier, which was seen as a bottleneck when processing larger amounts of data (a new need for 3D games). Thus, Hitachi synthesised a second revision with an extended multiplier unit and other features from Sega's checklist , leading to a new CPU called SH-2.
The two SH-2 chips found in the Sega Saturn
Even so, Sega couldn't stand still after hearing what choice of CPU its competitors went for. So, it asked Hitachi to step up the clock frequency of the SH-2 - an impossible task once the chip is already out for manufacturing. Luckily, Hitachi had another trick up their sleeve: multiprocessing. During the research phase of the SH, the team added minimal circuitry to allow the SH to work alongside other SHs within the same system simultaneously. Upon hearing that, Sega decided on a two-chip configuration for the Sega Saturn. And the rest is history.
The final product
Having explained the origins, let's take a look at the shipped product.
This console has not one but two Hitachi SH-2 CPUs running at ~28.63 MHz each . While both physically identical, they are placed in a master-slave state, where the first one may send commands to the second one. This can achieve some degree of parallelism, albeit both sharing the same external bus (which is prone to congestion).
Hitachi packaged different variants of the SH-2 and sold them as part of a series called 'SH7600'. All of them feature :
- The aforementioned five-stage pipeline and SuperH ISA. The latter has been extended with six additional instructions for specialised branching and arithmetic.
- An upgraded 32-bit multiplication unit, which now performs multiplication with 32-bit integers.
- A 32-bit external data bus that is shared across the two CPUs.
The specific chip selected for this console, the 'SH7604', contains the following additions :
- 4 KB of cache: Stores a small number of instructions and data previously fetched from memory to speed up future reads.
- A 32-bit division unit: Performs division with 32-bit integers.
- An internal Direct Memory Access (DMA) controller: Transfers data from memory without the intervention of the CPU.
- Support for little endian, enabling the CPU to understand values encoded in the opposite order. This is useful when external memory is shared with other processors.
It's worth pointing out that having two CPUs doesn't mean that games will work twice as fast! In practice, however, this requires very complex programming to efficiently manage CPUs that share the same bus. For instance, memory access should leverage the cache as much as possible.
The octopus architecture
Overview of the multi-subsystem model.
The Sega Saturn houses a significant number of processors (eight!). So, to avoid making them fight for resources, engineers grouped the circuitry into four separate subsystems:
- The CPU subsystem, where the main CPUs and memory reside. Truth be told, there's also an unusual third component. This is explained further down.
- The Video subsystem, comprising the graphics accelerators.
- The Audio subsystem, which can be considered a separate computer in its own right (you'll see more in the 'Audio' section of this article).
- The CD-ROM subsystem, a walled fortress owing to the copy-protection mechanisms implemented. These are explained further in the 'Anti-piracy' section.
It's worth noting that each subsystem is wired to a dedicated bus - except the Video and Audio ones, which share one.
A divided choice of memory
Overview of the main memory architecture.
The CPU subsystem contains a total of 2 MB of RAM for general-purpose use, called Work RAM (WRAM). But it's not that simple: this memory is split into two distinct blocks and, once again, each is accessed via different buses:
- The first block provides 1 MB of Synchronous DRAM (SDRAM). Due to its higher access speed, this block is also called WRAM-H. Its bus is shared with other components.
- The other megabyte is named WRAM-L, as it uses Dynamic RAM (DRAM) instead, resulting in lower rates. Its bus, however, is reserved for the main CPUs.
The third processor (and counting)
Surprisingly, it seems that the two SH-2 CPUs still weren't enough for Sega. So, to accelerate vector processing (at the cost of more complexity), the CPU group also houses an additional coprocessor, the Saturn Control Unit or 'SCU'.
The Saturn Control Unit in my motherboard revision.
This is a separate chip comprised of two modules :
- A Direct Memory Access (DMA) controller: Arbitrates access to WRAM-L across the three subsystems without the intervention of the CPUs.
- A Digital Signal Processor (DSP): Used as a fixed-point 'geometry unit'. Compared to the SH-2, it performs matrix/vectors calculations such as 3D transformations and lighting faster. However, it runs at half-speed and its instruction set is more complex. Furthermore, it depends on the SH-2's slow WRAM-L to fetch and store data (using the DMA).
To alleviate things, the SCU comes with 32 KB of Static RAM (SRAM) for local use.