Inside this console, we find the HuC6280, a chip developed by Hudson Soft that integrates two components. One of them is the CPU, which can operate at two speeds: ~1.79 MHz and ~7.16 MHz.
The HuC6280 chip on the PC Engine's motherboard
The HuC6280 is not an off-the-shelf component, like the Z80; it is instead a proprietary CPU designed by NEC. Its specification seems to replicate much of the behaviour of the famous MOS 6502 and WDC's 65C02. That being said, what does this mean for the programmer?
Before we start, I have already covered the MOS 6502 CPU in the NES article and described a 16-bit variant made by WDC and Ricoh in the SNES article, in case you wish to review them first.
The 65C02 is another modified version of the MOS 6502, made by Western Design Center (WDC). It is significantly more efficient due to its CMOS manufacturing approach. From the software perspective, the 65C02 introduces a handful of new instructions and modifies the behaviour of some existing ones .
While we could discuss more about the 65C02, I find it more relevant to focus on the features added by Hudson (which complement the 65C02), as they are critical to efficiently operate this console.
Compared to the 65C02, the HuC6280 includes :
- Additional opcodes, some of which target the components surrounding the CPU.
- An 8-bit I/O port for interfacing with external components.
- An interrupt controller to handle interrupts from other devices.
- A timer, which counts down from a specified value and, upon completion, dispatches an interrupt to the CPU.
Finally, there are 8 KB of Random-Access Memory (RAM) available for general-purpose use.
Memory access
One aspect I have not yet mentioned is that NEC also added a Memory Management Unit (MMU) adjacent to the CPU, allowing it to handle 21-bit addresses (remember the original 6502 only supports 16-bit addresses) . Thus, the amount of memory that can be accessed rises from 64 KB to 2 MB.
This MMU is very different from any modern-day MMU; I would say it is closer to a mapper. Having said that, the MMU in the PC Engine consists of eight 8-bit registers (called Mapping Register or 'MPR') that combine with the CPU's 16 address lines to form a 21-bit address bus.
Addressing approach of the MMU.
The process works as follows:
- The CPU can read from or write to any MPR using the special
TAMandTMAinstructions, respectively. - When physical memory is accessed, the MMU reserves the address lines A13-A15 from the CPU to select one of the eight MPRs.
- The final address is calculated by combining the CPU lines (placed at A0-A12) with the MMU lines (placed at A13-A20, where the output is the 8-bit value of the selected MPR), resulting in a 21-bit address.
Consequently, this MMU groups physical memory in 8 KB pages (13 CPU lines = 8 KB pages), which is the amount of memory the CPU can access without swapping or altering the MPR value.
Anyway, don't overwhelm yourself if this seems too complex (it is just an unconventional modus operandi some may find intriguing).