Mega Drive / Genesis Architecture

This console features two general-purpose processors from two distinct generations.

The leader

Firstly, we've got a Motorola 68000 running at ~7.6MHz. This is a new class of CPU which deserves a bit of story-telling...

Powering a decade

The Motorola 68000 or '68k' served as a generational leap in the history of microprocessors. Having learnt from the mistakes of the 6800, the company started over with a new team that could offer an affordable door to the 32-bit space. In there, much larger chunks of data could be processed, enabling programmers to provide new capabilities previously unknown to the consumer.

Apple's Macintosh (1984) and Lisa (1983). While at very different price points, both relied on the Motorola 68000 to display their innovative user interface.

Released in 1979, the 68k arrived in time to power the next decade of microcomputers. While initially struggling after losing IBM's contract to Intel, it didn't take long until other companies and start-ups adopted this chip to power their new inventions. Some implemented incremental improvements over their predecessors, while others achieved unthinkable capabilities, to name a few:

• A Graphical User Interface (GUI). New 68k-based products from Amiga, Apple, Atari and Sinclair debuted a novel form of user interaction. This time, founded on iconography, shapes and colours - and controlled with a 'Mouse'.
• Workstation applications: These cost-effective machines were now capable of processing huge workloads, with some degree of specialisation. This led to the rise of networking infrastructure, graphics design and research equipment - among others.
  • This also coincided with the arrival of UNIX-based operating systems to the masses, leading to an uneasy proliferation of 'standards' and subsequent lawsuits.

It's worth pointing out that much of this functionality wasn't new - it had simply been reserved for the costly minicomputers or prohibitive mainframes. The milestone lies in the fact that all of this could now be accessed from the typical office or household.

The Motorola 68000 chip on the Mega Drive, this one is second-sourced from Hitachi.

By the end of the 80s, however, interest in the 68000 faded in favour of a new wave of RISC CPUs. Yet, prices had come down enough for companies like Sega to take an interest in bringing it to the console market.

Features

Having set the scene, let me tell you what the 68000 provides :

• The 68000 Instruction Set Architecture (ISA): A new instruction set with plenty of features, including a set of multiplication and division opcodes. Some instructions are 8-bit long (called 'byte'), others are 16-bit long (called 'word') and the rest are 32-bit long (called 'long-word').
• Sixteen general-purpose 32-bit registers. Bear in mind, this CPU splits the set into eight 'data registers' (where arithmetic computations may be performed) and eight 'address registers' (exclusively used for storing memory addresses).
  • Nevertheless, this is a big step, considering the 6502 and Z80 only provide 8-bit registers.
• A 16-bit Arithmetic Logic Unit (ALU): Meaning it needs extra cycles to compute arithmetic operations on 32-bit numbers, but it's fine on 16-bit/8-bit ones.
• An external 16-bit data bus: As you can see, while this CPU has some '32-bit capabilities', it hasn't been designed to be a complete 32-bit machine. The width of this bus implies better performance when moving 16-bit data around.
  • Interestingly enough, Motorola debuted a complete 32-bit CPU, the 68020, four years before this console's release. But I imagine costs would've skyrocketed had Sega chosen the latter chip.
• A 24-bit address bus: This means that up to 16 MB of memory can be accessed. Memory addresses are still encoded with 32-bit values inside the CPU (the upper byte is just discarded).

If you wonder the reason behind using 24-bit addresses in a CPU that can handle 32-bit words: the equipment of that era was hardly asking to manage 4 GB of memory. Given that implementing unused lines is costly in terms of both performance and money, Motorola reached a sensible compromise with 32-bit registers and 24 address lines, preparing developers for the arrival of the full 32-bit CPU (the 68020) five years later.

A peculiar instruction set

Before the RISC revolution, there was a prior school of thought that attempted to consolidate how instruction sets were designed. In essence, consumer CPUs of the 70s (like the 6502 or the 8080) provide instructions that have already predefined how memory can be accessed (this is called the 'addressing mode'). A choice of multiple addressing modes enables the CPU to handle different use cases. However, the number of addressing modes tends to proportionally increment the complexity of the instruction set.

To remedy this, with the 68000, Motorola sought to unify most of its instructions. It did so by detaching the instruction function (the 'opcode') from the addressing mode, making the latter just another parameter (or 'operand'). In doing so, developers could now use the same opcodes with their addressing mode of choice (based on their needs).

As a simple example, to move data around:

• The MOS 6502 and WDC 65816 offer LDA, STA, LDX, STX, LDY, and STY opcodes. The choice depends on the direction of information (whether from register to memory or vice versa) and the specific register involved.
  • Additionally, in the WDC 65816, the parameter specifying the size of data (8-bit or 16-bit) resides in a separate register, requiring additional instructions (SEP and REP) to change it.
• In contrast, the Motorola 68000 provides a single MOVE opcode; its operands specify the origin, destination, size and addressing type.

This principle is called instruction set orthogonality, and it greatly influenced the new generation of CPUs in the late 70s, but quickly dissipated as RISC designs took over, effectively shifting the burden onto compilers. In any case, the Motorola 68k series enjoyed great popularity during the 80s decade, and it wasn't until the early '90s that companies started the switch to another vendor.

The Mega Drive's role

Within this console, the 68k serves as the 'main' CPU and it's tasked with managing game logic, handling I/O and performing graphics calculations.

Consequently, the external bus is physically connected to :

• 64 KB of general-purpose RAM.
• Cartridge ROM (up to 4 MB).
• Two Controllers.
• The Video Display Processor's registers, ports and DMA.
• Motherboard's registers (identifies the console).
• Expansion ports (used for 'future' accessories).
• The second CPU's RAM, intermediated by a bus arbiter.
• The Texas Instruments SN76489 (a PSG, acting as the second sound chip).

The second banana

There's another CPU fitted in this console: a Zilog Z80 running at ~3.5 MHz. This is the same processor previously analysed in the Master System article.

With the Mega Drive, however, the Z80 was mainly designated for sound control. Thus, its 16-bit address space comprises the following :

• 8 KB of RAM.
• The two sound chips available.
• A dynamic chunk of 32 KB mapped to the 68000's address space, selectable via a 'bus arbiter'.
  • In practice, however, the only reliable area to access here is the cartridge ROM .

Finally, it's important to note that both CPUs can run in parallel... under certain constraints, the next paragraphs explain more.

Memory available

The main CPU contains 64 KB of dedicated RAM to store general-purpose data and the Z80 contains 8 KB of RAM for sound-related operations.

Intercommunication

Sega chose two independent processors that have no awareness of each other, so how can games manage both at the same time? Well, the main program is executed on the 68000, and this CPU can subsequently write to the Z80's RAM. So, the 68000 can send a program to the Z80's RAM and instruct the Z80 to load it (by sending a reset signal to the Z80) . Once the Z80 is under control, it can then be used to manage the sound subsystem and move memory around using the previously described method - all while the 68000 handles other operations.

Memory architecture of the Mega Drive/Genesis.

There is one caveat, however: because one CPU must step into the other's bus, both CPUs cannot access the same bus at the same time. To address this, an extra component called Bus Arbiter is operated to stall either processor, enabling memory manipulation without any hazards.

It's worth noting that this design can underperform if not managed properly, so games have to take special care of the bus arbiter to ensure that neither CPU is stalled for longer than necessary.