Things were progressing smoothly for Hitachi; their iconic SuperH chips had found multiple clients, and the company was now ready for a fourth instalment of the series. Their new entry would combine embedded capabilities with functionality enjoyed by 3D games.
Sega, being one of the early adopters of the SuperH, unsurprisingly selected Hitachi's latest shipment to power their new console. Hence, the Dreamcast carries an SH-4 CPU running at a whopping 200 MHz . Also, to address previous shortcomings, there's only one fully equipped CPU.
The offering
That being said, what's interesting about this new processor?
Well, to start with, the SH-4 serves as a superset of the previous models, meaning it inherits all the existing features of the SuperH line, including a 32-bit RISC architecture, a 5-stage pipeline, and a 16-bit instruction set. Alas, it also inherits control hazards.
The SH-4 chip.
On top of that, as the next-generation CPU, it debuts many improvements that extend beyond the scope of embedded applications :
- A 2-way superscalar pipeline: A novel parallelism technique in which the CPU can process more than one instruction (two, in this case) in each stage of the pipeline. This results in more instructions executed per second.
- Behind the scenes, the CPU distributes the two instructions to two different (and available) execution units. Therefore - with the exception of a very small group - all instructions must be of different types (i.e. branching, arithmetic, etc.) to be parallelised . Otherwise, they can only be executed sequentially. Be that as it may, the SH-4 also exhibits a subset of instructions that can never be parallelised, as they contain too many dependencies to make it feasible.
- 8 KB instruction cache and 16 KB data cache: This ratio is rather curious, as consoles typically include more instruction cache than data cache. However, the SH-4 allows the data cache to be split into two sections: 8 KB of scratchpad memory (fast RAM) and 8 KB of data cache.
Special work
Common chores of a game-console CPU include handling the game's logic, running the enemy AI, and keeping the GPU fed with drawing tasks.
With the Dreamcast, you will see that the GPU only covers the tasks of a rasteriser. So, the CPU must get involved with the majority of the graphics pipeline. This means the CPU will be processing vast amounts of geometry data (such as computing animations and perspective transformations). Now, to ensure the CPU can sustain this role, Sega and Hitachi collaborated to incorporate two crucial extras into the SH-4.
The first addition is a dedicated 64-bit Floating-Point Unit (FPU). This component computes 32-bit decimal numbers (the so-called 'single-precision' or 'floats') or 64-bit ones (the 'double-precision' or 'doubles' type) in accordance with the IEEE-754 standard. Its register file is made of thirty-two 32-bit registers, but they can also be combined into a different group of sixteen 64-bit registers; this is what enables the unit to operate on doubles.
If that wasn't enough, Hitachi took a step forward with the FPU and implemented extra logic to form another register group, this time made of eight 128-bit registers. In it, each register now stores four 32-bit floats or, in other words, 128-bit vectors. This format is optimal for graphics-related operations.
To make good use of the new vectors, the FPU includes specialised instructions for operating on them, much like those provided by the Saturn Control Unit, except the industry is now a bit more standardised. These new instructions constitute what is often known as Single Instruction Multiple Data (SIMD) and may perform the following algebraic operations:
- Dot product.
- Sum of squares.
- Matrix multiplication.
The second addition is the SH-4's external bus, which is now 64-bit wide, enabling the CPU to transfer pairs of 32-bit values at the same time. This is another improvement that adds up to the overall performance of this CPU.
Main memory
The Dreamcast houses 16 MB of Synchronous DRAM (SDRAM), and it's directly connected to the CPU using a 100 MHz bus (half the CPU speed).
Main memory layout.
Conversely, the memory's data bus is only 32 bits wide . Does this mean the CPU's shiny 64-bit bus is wasted? No, because the RAM is arranged as two 8 MB banks, with each chip connected to half of the CPU's bus lines.
Customised access
To access this memory, the CPU allocates a 29-bit physical address space together with a Memory Management Unit (MMU) to provide 32-bit virtual addressing . Additionally, thanks to the inclusion of a Translation Lookaside Buffer (TLB), programmers can use 32-bit addresses without incurring performance penalties.
Now, since only 29 bits are used to access memory, the remaining three bits are leveraged to provide memory protection, alter the memory map, and bypass the cache .
Ultimately, programmers may decide whether to use these features. Games for this system certainly don't require memory protection, and the MMU must be manually enabled during boot.
Large package deliveries
When it comes to transferring large amounts of data to, let's say, feed the graphics chip with geometry, the SH-4's mov.l instruction can only operate up to 32-bit chunks (the size of the CPU's main registers) at a time. This means that wide blocks would require many individual mov.l calls. Consequently, the memory bus would be congested with unnecessary overhead.
Sega previously alleviated this with the Saturn Control Unit. Now, with the Dreamcast, the same CPU can additionally perform memory transfers using burst transactions: the SH-4 houses a 32-byte queue that can be filled with data, and then commit as a single big transfer . Nevertheless, the programmer is in charge of filling the queue, assigning the destination, and triggering the exchange.
Moreover, to avoid stalling the CPU while the queue is being transmitted, a second one is available to alternate.
All in all, this is very similar to the traditional Direct Memory Access (DMA) model - which the Dreamcast also features. However, burst transactions are simpler to operate albeit less versatile (the queues can only write data from the CPU to the outside). This console's DMA controller, on the other hand, supports variable-length transfers, multiple data sizes, and provides four channels for parallel operations (with many restrictions) .
No UMA but...
While this system is not built around the strict Unified Memory Architecture (UMA) like a well-known competitor, it does delegate I/O access to the GPU. This implies that whenever the CPU has to fetch anything beyond its dedicated RAM or the serial interface (which is also connected), it must issue a request to the GPU and wait if necessary.
The CPU also provides a unique functionality called Parallel Input/Output (PIO). It's used to manipulate multiple I/O locations at the same time. Sega wired these pins so that the CPU can control the GPU's video mode - I explain more details in the 'Graphics' section.
End of the line
Even with all the advantages described, I'm afraid the SuperH series didn't progress significantly after its last major adopter, the Dreamcast, left the stores. Following the popularity of the SH-4, Hitachi (and later Renesas Electronics, the current owners) were unable to replicate the same level of success, and considering the embedded/handheld market has since favoured ARM (thanks to StrongARM), I don't see Renesas continuing Hitachi's invention anytime soon.
The encouraging aspect of computing, however, is that technological progress often spreads beyond the boundaries of individual brands and companies. For instance, the SH's compressed-instruction technique lives on ARM's Thumb mode (a secondary 16-bit instruction set) . Furthermore, in 2012, a volunteer-driven initiative began work on a modern, SuperH-compatible CPU, called the 'J2' .